辅导 Sample Questions I辅导 Web开发

Sample Questions I

1. Give the performance equation (ignoring memory system effects) discussed in the class and explain its components.

2. The following measurements have been made using a simulator for a design that is projected to have a clock rate of 1GHz. What is the design’s CPI?

3. What happens to CPI if we shave one cycle off the branch time?

4. Assume that an optimized version of the design above has been implemented which doubles the projected clock rate to 2 GHz but also doubles the CPI of each instruction class except stores. Which design is faster, the 1GHz version or the 2 GHz version, and by how much (the 1 GHz version is the one in question B, not the one in C)?

5. Consider the following loop instruction sequence:

Loop:    add $3, $3, $2

lw $4, -100($3)

beq $3, $4, Loop

Suppose this loop executes exactly 3 times (iterations). Further assume that we have 5 execution stages, Instruction fetch, reading resource from register file, performance and ALU computation, reading or writing memory, storing data back to the register file and that the clock times for these stages are 4ns, 1ns, 2ns, 4ns, 1ns, in that order. What is the CPI and CCT of the 3-iteration loop in a single-cycle machine?

6. For the same scenario in the above question, what is the CPI and CCT in 3 iterations in a multi-cycle machine?

7. Recall the MIPS instructions type (R, I, J) we discussed. The 32-bit formats are shown here:

Indicate the bits for each part and explain the functionalities of op, funct, and immediate fields.

8.  The individual stages ofa pipelined datapath have the latencies and the instruction percentage has the mix as shown in the tables below.

What is the fastest possible clock time (in ps) for a non-pipelined, single-cycle MIPS datapath and for a 5- stage pipelined MIPS datapath, respectively?

9. How are memory structural hazards avoided in our 5-stage MIPS pipelined datapath?

10. Consider the following instruction sequence executed on a 5-stage pipeline in-order machine. sw $2 100($3)

sub $5, $2, $4

Indicate, on the figure below, the components that will be activated to execute lw and add instructions above, using circle (o) and star (*) to denote lw and add, respectively.