EECS 31L: Introduction to Digital Logic Laboratory (Spring 2025)
Lab 5: Single-Cycle RISC-V Processor
(Revision: v1.0)
Due: Tuesday, June 10, 2025 (11:59 PM)
In this lab, we will complete the design of our single cycle RISC-V processor. As you see in Figure 1 there are three sub-modules in this processor.
Figure 1: Submodules in a RISC-V processor
We have designed the Datapath in Lab4. The Controller takes Opcode from the Datapath and produce five control signals (MemtoReg, MemWrite, MemRead, ALUSrc, RegWrite) and a 2-bits ALUOp. The ALU-Controller takes Funct3 and Funct7 from the Datapath and ALUOp from the Controller and produces a 4-bits operation input (ALUCC) for the Datapath.
In the first part of this lab, we will design the two remaining sub-modules (Controller and ALU Controller). Then in the second part, we will use these submodules and the datapath to complete the processor.
Before starting the design process, please review the instruction set we have already implemented:
Table 1 : Instruction Set.
1 Lower Level Modules
1.1 Controller
From figure 1, you see the control signals which we used in the datapath design are driven by a module named “Controller.” The input to this module is a 7-bits Opcode field of the instruction (comes from the Datapath). The outputs of the control unit are:
• Two signals that are used to control multiplexers in the Datapath (ALUSrc and MemtoReg)
• Three signals for controlling reads and writes in the register file and data memory in the Datapath (RegWrite, MemRead, and MemWrite)
• A 2-bits control signal for the ALUController unit (ALUOp)
Here is the block diagram of the Controller.
Figure 2 : Controller.
With the information in Table 2, we can design the Controller.
• The MemtoReg signal is ‘0’ for all instructions except for the “Load” instruction
• The MemWrite signal is ‘0’ for all instructions except for the “Store” instruction
• The MemRead is also ‘0’ for all instructions except for the “Load” instruction
• The ALUSrc is ‘1’ when the opcode is “0010011” or “0000011” or “0100011”. For these instructions, source B operand comes from the imm Gen. For other instructions with opcode “0110011”, ALUSrc is ‘0’ Because both of the Source operands of the ALU come from the register file.
• RegWrite is ‘1’ except for the “Store” instructions. This is because for all of these instructions we want to write back the result to the register file.
• The ALUOp(1 downto 0) is “10” when the opcode is ”0110011” and ”00” when the opcode is “0010011”. It is also “01” for the “Load” and “Store” instructions with opcodes “0000011” and “0100011” respectively.
Table 2 : Control Signals.
Use this code for the module part of the Controller. Module definition of your code should exactly look like the given one.
Code 1: Controller
`timescale 1 ns / 1 ps
// Module definition
module Controller (
Opcode ,
ALUSrc , MemtoReg , RegWrite , MemRead , MemWrite ,
ALUOp
);
// Define the input and output signals
// Define the Controller modules behavior.
endmodule // Controller
1.2 ALUController
The inputs to the ALUController are the ALUOp, Funct3, and Funct7. ALUOp comes from the Con troller and Funct3 and Funct7 come from the Datapath. The output of the ALUController is the 4-bits operation code which goes to the ALU CC input of the datapath. You see the block diagram of the ALU-Controller in figure 3.
Figure 3 : ALUController.
Table 3 shows the list of the instructions and their operation code.
Table 3 : Instruction and the operation code.
We need to find a relation between the inputs and the output of the ALUController. Table 4 shows this relation.
Table 4 : The truth table for the 4 operation code.
“-” in Table 4 means there could be any values there.
Here you see the equation for the first bit of the operation as an example:
assign Operation [0]=
(( Funct3 == 3'b110 ) || (( Funct3 == 3'b010 ) && ( ALUOp [0] == 1'b0 )))
? 1'b1 : 1'b0 ;
Here is the sample code for the ALU Controller.
Code 2: ALUController
`timescale 1 ns / 1 ps
// Module definition
module ALUController (
ALUOp , Funct7 , Funct3 , Operation
);
// Define the input and output signals
// Define the ALUController modules behavior.
endmodule // ALUController
1.3 Datapath
Use the Datapath module we have already designed in the Lab4. Check your design to ensure that your datapath from Lab 4 is working correctly.
Code 3: Datapath
`timescale 1 ns / 1 ps
module data_path #(
parameter PC_W = 8 , // Program Counter
parameter INS_W = 32 , // Instruction Width
parameter RF_ADDRESS = 5 , // Register File Address
parameter DATA_W = 32 , // Data WriteData
parameter DM_ADDRESS = 9 , // Data Memory Address
parameter ALU_CC_W = 4
// ALU Control Code Width
)(
input clk ,
input reset ,
input reg_write ,
input mem2reg ,
input alu_src ,
input mem_write ,
input mem_read ,
input [ ALU_CC_W -1:0] alu_cc ,
output [6:0] opcode ,
output [6:0] funct7 ,
output [2:0] funct3 ,
output [ DATA_W -1:0] alu_result );
// next pc
// instruction memory
// register file
// sign extend
// alu
// data memory
endmodule
2 Higher Level module
2.1 Processor
We have designed the three sub-modules of the processor (Datapath, Controller, ALUController) and now we want to use them to design a single cycle processor. Create a new source and define these three components and connect them to make the processor.
Here again, you see the processor diagram. Blue lines are some wires which we used to connect the sub-modules. Define these blue lines as wires and connect the components to complete the Processor.
Use this code for the Module part of the Processor.
Code 4: processor
`timescale 1 ns / 1 ps
module processor
(
input clk , reset ,
output [31:0] Result
);
// Define the input and output signals
// Define the processor modules behavior.
endmodule // processor
After finishing Processor design the sources window in the Vivado should look like this.
Important: we want you to have separate source files for each of the sub-modules.
2.2 Test the Processor
To test our code we only need to provide 2 inputs (clk and reset) and then read the outputs to see if they are as expected or not. In every rising edge of the clock, the processor will read a new instruction from the instruction memory and send the result to the output. Use the code below as test bench.
Code 5: tb processor
`timescale 1 ns / 1 ps
module tb_processor ();
/** Clock & reset **/
reg clk , rst ;
wire [31:0] tb_Result ;
processor processor_inst (
. clk ( clk ) ,
. reset ( rst ) ,
. Result ( tb_Result )
);
always begin
# 10;
clk = ∼clk ;
end
initial begin
clk = 0;
@ ( posedge clk );
rst = 1;
@ ( posedge clk );
rst = 0;
end
initial begin
dumpf ile(”test.vcd”);dumpvars ;
end
integer point =0;
always @ (*)
begin
#20;
if ( tb_Result == 32 'h00000000 ) // and
begin
point = point + 1;
end
#20;
if ( tb_Result == 32 'h00000001 ) // addi
begin
point = point + 1;
end
#20;
if ( tb_Result == 32 'h00000002 ) // addi
begin
point = point + 1;
end
#20;
if ( tb_Result == 32 'h00000004 ) // addi
begin
point = point + 1;
end ;
#20;
if ( tb_Result == 32 'h00000005 ) // addi
begin
point = point + 1;
end ;
#20;
if ( tb_Result == 32 'h00000007 ) // addi
begin
point = point + 1;
end
#20;
if ( tb_Result == 32 'h00000008 ) // addi
begin
point = point + 1;
end
# 20;
if ( tb_Result == 32 'h0000000b )// addi
begin
point = point + 1;
end
# 20;
if ( tb_Result == 32 'h00000003 ) // add
begin
point = point + 1;
end
# 20;
if ( tb_Result == 32 'hfffffffe ) // sub
begin
point = point + 1;
end ;
# 20;
if ( tb_Result == 32 'h00000000 ) // and
begin
point = point + 1;
end ;
# 20;
if ( tb_Result == 32 'h00000005 ) // or
begin
point = point + 1;
end ;
# 20;
if ( tb_Result == 32 'h00000001 )// SLT
begin
point = point + 1;
end ;
#20;
if ( tb_Result == 32 'hfffffff4 ) // NOR
begin
point = point + 1;
end
#20;
if ( tb_Result == 32 'h000004D2 ) // andi
begin
point = point + 1;
end
#20;
if ( tb_Result == 32 'hfffff8d7 ) // ori
begin
point = point + 1;
end
#20;
if ( tb_Result == 32 'h00000001 ) // SLT
begin
point = point + 1;
end ;
# 20;
if ( tb_Result == 32 'hfffffb2c ) // nori
begin
point = point + 1;
end ;
# 20;
if ( tb_Result == 32 'h00000030 ) // sw
begin
point = point + 1;
end ;
# 20;
if ( tb_Result == 32 'h00000030 ) // lw
begin
point = point + 1;
end ;
$display ("%s%d " ," The number of correct test cases is :" , point );
end
initial begin
# 430;
$finish ;
end
endmodule
Check the output (Result) to see if they are correct. Put a screenshot of the wave in your report and clearly annotate the result.
3 Assignment Deliverables
New Testbench Requirements:
To make the grading more efficient, please add the following initial block in your testbench module:
Code 6: Testbench Initial Block
initial begin
$dumpfile (" test . vcd ");
$dumpvars ;
end
Submission Requirements:
Your submission should be in a *.zip file and should be submitted to Gradescope. The ZIP file should include the following items:
• Source Code: Block designs and testbench:
(tb processor.v, processor.v, Controller.v, ALUController.v, FlipFlop.v, InstMem.v, RegFile.v, Imm-Gen.v, Mux.v, ALU.v, DataMem.v, Datapath.v).
• PDF Report: A report in the PDF format including the simulation results.
Compress all files (*.v files + report) into one ZIP file named “lab5 UCInetID firstname lastname.zip” (note: UCInetID is your email user name and it is alphanumeric string), e.g., “lab5 sitaoh sitao huang.zip”, and upload this ZIP file to Gradescope before deadline.
Note 1: To make the grading process more efficient, please use the exact same module names, port names, and file names as specified in this manual. You will lose points if you use different names. Use the code skeletons given in the lab manual. The module part of your code (module name, module declaration, port names, and port declaration) should not be changed.
Note 2: Start working on the lab as early as possible.
Note 3: It is fine to discuss the lab with others, but please write the code by yourself.