Department of Electrical & Computer Engineering
High Perfromance Digital Circuit Design ECE 123/223
Midterm Exam, November 24, 2025
1. (10 points) Question 1: 10points
Which of the NAND gates in figure 1(a) might be made asymmetric in order to yield the fastest design, explain your choice with clear calculations? Assume that both inputs should be equally favored. Asymmetric does not mean just skewed, to aid your analysis you may use the figure 1(b), where s is the symmetry factor and γ is the P:N ratio. You can assume the P:N ratio is 2:1. Does your answer depend on the electrical effort of the “gate”?
(a) NAND Based XOR
(b) Asymmetric NAND
Figure 1: Asymmetric NAND gate based logic circuits
2. (10 points) Question 2: 10points
You recently joined the company NotVDIA as a circuit designer and find that in the new process they are using the transistor contact resistance is 0.25 × Rc , the contact resistance for a minimum width device, which has a single contact. The contact resistance value is the same for both the PMOS and the NMOS. From your ECE 122A class you know the contact resistance scales inversely with the number of contacts increases in increments of minimum width (Wmin )i.e. a device with 2 * Wmin has 2 contacts, but a device with
2.5Wmin still has only two contacts. You can model the transistor as shown in figure 2a. The capacitances shown are the source drain capacitances that scale with width and the output load is the parasitic capacitance due to the contact resistance which is also proportional to the width (since it is dependent on metal length not number of contacts.
It turns out the effeective resistance of a NMOS of minimum width is ReffN = 1.5 * Rc , where Rc is a process dependent constant. You are tasked to design an inverter with equal rise and fall times (see figure 2b), given the P:N ratio is 2:1. What is the sizes of the PMOS and NMOS?
Figure 2: PMOS and NMOS with contact resistance
3. Question 3: 40points
Consider the inverter buffer circuit shown in figure 3, used to drive a signal to four dif- ferent loads via interconnects of differing lengths. The interconnect has 0.1Ω/□ and a capacitance of 0.02fF/µm, and a gate capacitance/unit width of 0.8fF/µm.The mini- mum width of the device in this process is 0.1µm. The P:N ratio is 3:1 in this process and the tp0 is given as 8 ps.
Figure 3: Interconnect Branch
(a) (15 points) If the interconnect width is 0.1µm, sizes the inverters for optimal path delay.
(b) (25 points) Choose the interconnect widths for the most optimal path delay. The width can be increased in steps of 5nm, given the minimum width of the interconnect is 0.1μm
4. Question 4: 40points
Consider the 16-bit output prefix adder shown in figure 4(a), the output of the sum bits drive 8Cinv and the carry-out drives 32Cinv . Note the input is 15-bits and the out is 16-bits. The last bit is the carry-out. The group generate and propagate logic blocks are shown in figure 4(b). Note: The -1 bit is the bit 0 of the input.
(a) 16-b Prefix Adder
(b) Logic Blocks Corresponding to the Legend in the main figure
Figure 4: A 16-b Prefix Adder
(a) (5 points) Clearly identify and draw the critical path (i.e the longest path delay) of this adder
(b) (35 points) Size the path for optimal delay, given the input can only drive a maxi- mum of 16Cinv
For all problems, we are using the 0.18µm technology node. The maximum supply voltage for this technology is Vdd (Max) = 1.8 V For hand calculation you may use the following parameters
NMOS:
PMOS:
You may find the following equations useful
For an inverter chain containing N inverters:
For a logic path containing N logic gates: