辅导 ELEC ENG 3088/7088 Computer Architecture Assignment — RISC-V RV64I ISS — Stage 1辅导 C/C++程序

ELEC ENG 3088/7088 Computer Architecture

Assignment — RISC-V RV64I ISS — Stage 1

Your task for this assignment is to develop an instruction set simulator (ISS) for the RV64I subset of the RISC V instruction set. An instruction setsimulator is a program used by computer architectsto simulate execution of a computer’s instructions. It contains representations of the computer’s memory and the internal registers of the CPU. It respondsto commandsthat specify initialisation and inspection of the memories and registers, and control execution of instructions.

The RISC-V instruction set is described in “The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture”,available on the course web site. The RV64I subset is described in Chapter 4 of the Instruction Set Manual, building on the RV32I subset described in Chapter 2. The instruction encoding is summarised in Chapter 24. For this assignment, you should implement just the RV64I base integer instruction set, with the following exceptions:

• FENCE: This instruction should be decoded as a legal instruction but perform. no operation.

• ECALL, EBREAK: These instructions should be decoded as legal instructions, but a message should be displayed indicating they are unimplemented.

For load and store instructions, you can assume that the effective address is properly aligned. Do not implement mis- aligned loads or stores. For any fetched instruction word that does not represent an RV64I instruction, a message should be displayed indicating the instruction is illegal. In Stage 2, you will implement exception handling, which will be used for illegal instructions.

We have provided a skeleton program on the course web site for you to use as a starting point. The program is written in C++ and is provided via GitHub. The skeleton program implements processing of command-line options and input commands. Yourtask isto implement classestomodelthe processor andmemory. Head- er files are provided showing the member functions required. You can add additional classes if you need to.

The only command-line option you need to implement at this stage is the -v option to enable verbose output. If the -v option is specified on the command line, your program can display debugging information. If the option is omitted, your program should display only the output required for each command. Your program must format that output exactly as specified below, since the assessment process will compare you output with expectedoutput.

The rv64sim program reads commands from the standard input stream, one command per line. The commands are listed in Table 1.

Each command may be followed by a comment, starting with the ‘#’ character and extending to the end of the line. Blank lines are permitted, as are lines containing only a comment.

The initial value of all processor general purpose registers should be 0, and the initial value of the PC should also be 0. The memory should appear to have all locations initialized to 0. Your program should count the number of instructions executed. This will be reported on completion of execution.

During simulated execution, you should count the number of simulated clock cycles, in addition to the number of instructions executed. You should use the following cycle counts for various instruction types:

• Conditional branch instruction: 2 cycles if the branch is taken, or 1 cycle if the branch is nottaken.

• Unconditional branch instruction: 2 cycles.

• Load instruction: 3 cycles.

• Store instruction: 2 cycles.

• All other instructions: 1 cycle.

Table 1 rv64sim commands

On completion of a simulation, if the -c option is specified on the command line, your program will report the total number of simulated clock cycles taken.

You can test your ISS by using the “m” command to set memory locations to the encoded value of RISC-V instructions, using the “pc” command to set the PC to the start of the code, then using the “.” command to execute the code. Alternatively, you can use the RISC-V GNU Compiler Toolchain (C compiler, assembler, linker, binutils; available at https://github.com/riscv/riscv-gnu-toolchain) to generate hex files to load into memory. We will use both of these processes when we assess your ISS.

Performance of an ISS program is important. Computer architects typically use them to develop code for embedded system, so they must be able to execute 100s of thousands of instructions per second. You should design your ISS with performance in mind. The skeleton program provided uses the native integer data types uint32_t and uint64_t to represent instructions and data, rather than using a dynamically allocated class-typed object orstring. When you implement the memory, you should not attempt to represent it using a large array of words. Since addresses are 64 bits, that would imply an array of 264 bytes. Instead, consider a representation that allocates blocks of memory on demand (that is, on the first read or write to an address within a block).

Please keep an eye on the Assignment forum on the course web site. There will no doubt be questions of clarification of requirements arising that we will answer there. We will also announce incremental releases of a test suite that you should use to test your program.

For the submission deadline, please refer to the course page on MyUni. There are two stages for the Assignment worth 20% of the course. Postgraduate students will have additional requirements in Stage 2.