ELEC373
Digital Systems Design
Assignment 4
NIOS II
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Module
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ELEC373
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Coursework name
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Assignment 4
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Component weight
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20%
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Semester
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2
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HE Level
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6
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Lab location
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PC labs 301, 304 as timetabled, at other times for private study
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Work
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Individually
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Timetabled time
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15 hours (3 hours per week – Tuesday 9am - noon)
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Suggested private study
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10 hours including report writing
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Assessment method
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Individual, formal word-processed reports (Block diagrams and ASMs can be hand drawn and scanned into the report)
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Submission format
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Online via CANVAS
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Submission deadline
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23:59 on Monday 13th May 2024
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Late submission
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Standard university penalty applies
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Resit opportunity
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August resit period (if total module failed)
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Marking policy
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Marked and moderated independently
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Anonymous marking
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Yes
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Feedback
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Via comments on Canvas
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Learning outcomes
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LO1: Ability to design digital systems using the ASM design method
LO2: Ability to implement digital systems using the Verilog Hardware Description Language
LO4: Ability to implement a SOPC system using Quartus Nios II.
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Marking Criteria
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Section
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Marks available
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Indicative characteristics
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Adequate / pass (40%)
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Very good / Excellent
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Presentation and structure
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20%
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• Contains cover page
information, table of contents, sections with appropriate
headings.
• Comprehensible language; punctuation, grammar and spelling accurate.
• Equations legible, numbered and presented correctly.
• Appropriately formatted reference list.
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• Appropriate use of technical, mathematicand academic
terminology and conventions.
• Word processed with consistent formatting.
• Pages numbered, figures and tables captioned.
• All sections clearly signposted.
• Correct cross-referencing (of figures, tables, equations) and citations.
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Introduction,
Method and
Design
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40%
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• Problem background introduced clearly.
• Evidence of a Top Down Design approach
• Conceptual Design Choices introduced.
• Design of each module follows a logical sequence.
• ASMs correspond to designs for each block.
• Software is clearly commented
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• Appropriate range of references used.
• Design decisions justified with alternatives given.
• Calculations shown in full, justifying and explaining any decisions.
• Correct ASM Syntax used.
• Well-structured Verilog Code
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Results
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30%
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• Simulation results present for each block and well annotated.
• Results of full system in both simulation and experimentally presented.
• Results for each task
accompanied by a commentary.
• Screenshots of results presented.
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• Tests indicate that there are no
problems caused by asynchronous inputs.
• Clear explanation of how the instructions operate correctly
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Discussion
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10%
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• Discussion on what worked and what didn’t.
• Critical assessment on the design – strength and
weaknesses
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• Discussion on how the system was fully tested.
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ELEC 373 Assignment 4 (2023-24) Synthesising the NIOS II Processor
Assignment Outline
In Assignment 3 you added some extra instructions to a MIPS processor which was then synthesised and executed on the DE2 board. This assignment aims to introduce you to a commercial synthesised processor targeted for Altera FPGAs, which allows the easy importing of peripherals and the use of an industry standard IDE for software development.
Assignment 4 is split into two parts, Parts A and B. The objective of Part A is to get you familiar
with QSYS, the NIOS II Processor and interfacing SRAM and SDRAM, on the Altera DE2 Board,
to the NIOS II processor you synthesise. Part B requires you to develop and test a Custom Instruction that will be implemented in the FPGA.
Part A - SRAM & SDRAM
The NIOS II hardware development tutorial synthesises aNIOS II processor with, 20 KB of on-chip memory, atimer, a JTAG UART, 8 parallel I/O pins and a system ID Component. Part A of this assignment requires you to interface the 512 KB SRAM and 8 MB SDRAM on the Altera DE2 Board to this design.
You should then test that the memory is functioning correctly by running the Memory Test programs available within the NIOS II IDE. You should modify the Memory Test Programme so that your
Name andID number are shown in the terminal window each time the memory is tested.
Hints
1. Initially use the altera_up_avalon_sram Controller (SRAM/SSRAM) for the SRAM interface
2. Use the SDRAM controller for the SDRAM Interface
3. Add a PLL to advance the clock for the SDRAM by 3ns compared with the system clock.
Part B - Custom Instruction
Part B requires you to develop a Custom Instruction to count the number of leading 1s (or 0s - see Table 1) in the 32 bit number passed to the instruction (for example 0xFF000000 would have 8 leading 1s and 0 leading 0s, whilst 0x00F00000 would have 0 leading 1s and 8 leading 0s). You should write a program to test your Custom Instruction. You should also develop a test routine in C or assembler that performs the same function as the Custom Instruction and compare the speed of the Custom Instruction against your software implementation.
Submission
You report should include the following:
1. Block diagram of BDF developed in Part A.
2. Table showing memory Map for Part A
3. Screen dumps of test results showing memory test programs working for SRAM and SDRAM
4. ASM(s) and Verilog code for your custom instruction in Part B
5. C/C++ for your test program of Part B
6. Screen dump showing the results of your program for Part B
7. Results showing a speed comparison between the Custom Instruction and your software implementation.
8. Explanation of your results.