2021/4/4 Assignment 3 description - COMP-3370-A01 - Computer Organization
1/9 Assignment 3 description
COMP 3370 - Computer
Organization
Assignment 3
Franklin Bristow
Winter 2021
Introduction
Questions
Part 1
Suggestions
Grading for part 1
Handing in
Appendices
Control unit state machine
Introduction
Now our simulator both functions and has a cache memory, so it works, and it
works “faster”.
The main missing thing with our simulator right now is persistence; programs
run, then eventually end, where the only persistence that we have from the
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execution of that program is whatever is printed out on standard output.
In this assignment, you’re going to be adding some persistence in the form of a
virtual hard drive, and the virtual hard drive is going to have a DMA controller to
facilitate moving data between main memory and the drive itself.
Questions
Part 1
Add a virtual hard drive with DMA to the sample solution for assignment 2.
We’re not going to be adding any new instructions, so your implementation will
have to support memory mapped I/O to initiate DMA transfers (setting the
registers of the virtual drive).
Consider the following in your implementation:
Add a phase following write-back for “handling interrupts” – this is where
your implementation will perform DMA transfers. In an ideal situation, the
CPU and the phases of execution wouldn’t need to explicitly model “handling
interrupts” (they would just get fired asynchronously), but we don’t want to
add the complexity of needing to use threads for this assignment, so we will
“monitor” for interrupts by adding this new phase.
While the only thing that would normally happen in an interrupt phase is that
the CPU would be notified that a transfer has completed, you’re actually
going to conduct burst transfers during this interrupt phase.
Your DMA transfers should be implemented as “burst” transfers, where the
CPU is “halted” during interrupt processing so that the DMA transfer can
occur. For each DMA transfer, the simulator will move 4 words of data
between the virtual disk and memory (possibly fewer words if there are not
that many left to transfer, e.g., only 2 words left to transfer will only transfer
2 words).
The “hard drive” is a total of 4096 words in size, and has 3 registers for
manipulating the drive. The registers are memory mapped to data
memory, where each register is mapped to memory locations 0, 1, and 2 as
follows:
Memory location 0 maps to the status register . The least
significant bit indicates whether we are performing a read or write
operation (a 0 indicates a read). The remaining bits are the count of the
number of words that must be transferred
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number of words that must be transferred.
This means that an instruction sequence like
MOVE R1,0 MOVE [R1],7
Says something like “write the value 7 to the HD status register (memory
map 0)”. The number 7 here (0b0111) says “We’re going to write 3
words” (least significant bit is 0b1, remaining bits are 0b011).
If the remaining bits (after the read/write bit) is non-zero, we still have
words to transfer during the interrupt handling phase. This means that
we’re using this register to track how many words are left to be
transferred (we’re only transferring up to 4 at a time with burst transfers).
This means that if the value in the status register is currently 0b0101, then
the DMA controller is writing (least significant bit is 1), and it still has 2
words to transfer (remaining bits are 0b10).
Memory location 1 maps to the HD address register . It contains
the drive address for performing the next word transfer. You don’t have to
worry about modelling tracks, sectors, etc, just treat this address as an
index into a contiguous array of words.
Note specifically that this means that the hard drive explicitly should not
be modelled as blocks in the same way that data memory and your cache
are modelled as blocks; the virtual hard drive explicitly is a linear,
contiguous array of words.
Memory location 2 maps to the memory address register . It
contains the memory address for performing the next word transfer. Note
that DMA sees memory as a contiguous region and doesn’t care about the
organization fror caching. Further note that you should not change
memory organization, because that would break the caching
implementation.
Your memory access support must catch read/write operations to these
memory locations and automatically map them to accesses of the
corresponding registers. Note that these are the worst locations to use
(memory mapped I/O normally uses high addresses) but this ensures that all
existing test programs are broken (see below).
Your simulator must maintain a persistent copy of the hard drive contents (as
a binary file) to allow for the persistent state to be loaded between runs of
the simulator. When your simulator launches it must look for the hard drive
file (it can be hard-coded) and, if found, load the drive contents from the file
(filli ith 0 FF if th ’ fil ) O it th i l t t it th
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(filling with 0xFFs if there’s no file). On exit the simulator must write the
current drive contents to the file.
As DMA transfers occur you must perform cache snooping with the writeinvalidate policy to ensure that the cache remains consistent with main
memory (i.e. cache contents can become invalid as we write to memory from
the hard drive).
You must also change the cache update policy to employ write through
instead of write update to ensure that we always write the latest data to
the hard drive.
Despite having an “interrupt phase”, we explicitly have not implemented
interrupt handling (again, we definitely do not want to deal with threads in
this assignment). Since there is no interrupt handling in the simulator, any
programs that run on this simulator need to employ polling to know if/when
a DMA transfer has completed. This specifically means that the program has
to poll the status register to check how many words are remaining to be
transferred.
A pre-compiled sample has been provided along with one sample program. Note
that this sample program does not necessarily completely test the expected
behaviours described above. You should also write your own sample programs to
evaluate the complete behaviours described above (read/write, polling for
completion, etc). You must submit this program as part of your submission
package.
The graders will be evaluating your assignment using three input files, the one
that’s provided, the one you provide, and one other that is explicitly not provided.
Suggestions
Since the sample program’s output to standard output has not changed, and
you are not expected to change the program’s output to standard output, you
may want to check/compare the contents of the virtual hard drive. The
sample program writes to a file called hd. You can use a program called
hexdump to pretty print binary files as hexadecimal output. I suggest that you
use the -C option (e.g., hexdump -C hd) to inspect and compare the contents
of the hard drive file that you create to the one that the sample simulator
creates.
Writing a binary file in C/C++ is straightforward, you can use fopen and
fwrite (you technically don’t even need to use a loop with fwrite).
Very explicitly do not bother checking to see if the file you’re writing exists
when you’re writing the virtual hard drive out; just blindly overwrite anything
that was there before.
The virtual hard drive is completely in the physical memory of your machine
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The virtual hard drive is completely in the physical memory of your machine
while the simulator is executing (e.g., it’s literally just an array). You explicitly
do not need to fwrite to the file every time you’re conducting a DMA write;
only write to the file at the end of the execution of the simulator (e.g., around
the same time you’re printing out memory to standard output).
Grading for part 1
There are a total of 20 points for part 1:
5 points for code quality and design:
0 points: the code is very poor quality (e.g., no comments at all, no
functions, poor naming convention for variables, etc).
1–3 points: the code is low quality. While some coding standards are
applied, their use is inconsistent (e.g., inconsistent use of comments,
some functions but functions might do too much, code is repeated that
should be in a function, etc).
4–5 points: The code is high quality, coding standards are applied
consistently throughout the code base.
10 points for implementation (5 × 2):
0 points: no implementation is submitted, the implementation is vastly
incomplete, or the code crashes when executed (this specifically means
that your code crashes with, for example, a Segmentation fault or Bus error, the assembly code is expected to crash as an exit condition).
1–2 points: implementation is significantly incomplete, for example,
only one part of persistence might be implemented (e.g., only the virtual
hard drive is implemented), but DMA itself is substantially incomplete.
3–4 points: implementation is mostly complete, for example, the basic
operations are present (e.g., transferring between hard drive and
memory), but different parts may not be implemented correctly (e.g.,
write invalidate).
5 points: implementation of the DMA system is complete.
3 points for drive contents
1 point for the drive contents of the provided sample program,
1 point for the drive contents of the unpublished sample program,
1 point for the drive contents of the sample program you provide.
2 points for your sample program itself: does it actually evaluate all of the
different behaviours for the DMA system described (e.g., read/write, polling,
etc)
Notes:
If your code does not compile on rodents.cs.umanitoba.ca with a single
invocation of make (that is, the grader will change into the appropriate
directory and issue the command make with no arguments), you will receive a
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score of 0 for this assignment. If your submission does not have a Makefile,
that’s effectively the same as submitting code that does not compile.
Forget how to make a Makefile? Never knew how to make a Makefile?
Thankfully, you can go to https://makefiletutorial.com and find some
very easy to use basic examples.
You can use g++ or clang++, there are no restrictions on which compiler
you use beyond the compiler being installed on rodents.
While we’re not checking for warnings or DbC, both are your friends.
Handing in
The following should be in your package:
1. Your simulator .cpp file,
2. The sample program that you write (a .asm and .dat file),
3. A Makefile that builds your simulator.
4. A README describing your sample program.
Appendices
Control unit state machine
Remember that the two “states” Cache read and Cache write aren’t exactly
“states”, cache reading and writing are part of the existing states (e.g., writing to
cache is part of the Write Back state), but these have been visualized in the state
machine to demonstrate when they happen.
You explicitly must not add the cache-related states to your program.
You explicitly must add the “interrupt handling” phase to your program, where
DMA transfers actually happen.