COMP1027 – Computer Fundamentals
School of Computer Science – Coursework Issue Sheet
Session Semester August
Module Name Computer Fundamentals Code COMP1027
Module Convenor(s)
(CW Convenor in Bold)
Amr Ahmed
Coursework Name Exercise 1 (part 1 of the Coursework) Weight 10%
Deliverable
(a brief description of what is
to be handed-in; e.g.
‘software’, ‘report’,
‘presentation’, etc.)
Please see details (6 pages) in the assignment document (below), including
list and description of the required tasks and details of the submission.
Format
(summary of the technical
format of deliverable, e.g.
“C source code as zip file”,
“pdf file, 2000 word max”,
“ppt file, 10 slides max”, etc.)
As explained in the “Submission Details”, P.6.
All the required files (.hdl , .tst , *.cmp).
Issue Date 7
th October 2020 (tasks have already started in the lab on 1st October)
Submission Date October 2020 (22:00)
th 16
Submission Mechanism Online, through moodle.
Late Policy
(University of Nottingham
default will apply, if blank)
Feedback Date Usual 15 working days.
Feedback Mechanism Online, on moodle.
Instructions See the Ex1 document
Assessment Criteria All chips will be tested through testing scripts.
Developed and working properly full mark of the component
(unless there is any concern of any cutting corners/plagiarism,….etc.).
Missing any required file(s), using different formats, naming,…etc. will attract
presentation penalty.
COMP1027 – Computer Fundamentals
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Exercise 1: Elementary Logic Gates & Combinational Circuits
(Covering Teaching Weeks 2-3)
[ Submissions are Assessed, worth 10%]
Introduction
In total, this coursework (lab work, split into multiple submissions, and assignments) is worth
50% of your final mark.
Each of the weekly exercises will get you to build different sections of the HACK computer,
although some of the more complex components will be provided for you.
Preliminaries
We are going to work through some of the nand2tetris projects which enable us to build
simulations of the pieces of hardware that form a computer system using the supplied
Hardware Simulator.
First, you should have downloaded the nand2tetris software and successfully used
the Hardware Simulator. Follow the given lab briefing and guidance.
Inside the nand2tetris directory, alongside the tools directory you should also find
a projects directory that contains a series of sub-directories, one for each project.
Each directory contains the files that are the starting point for each project.
The first task, which is not assessed, is to get familiar with designing logic circuits in the
Hardware Simulator
You will almost certainly find it helpful to refer to Chapter 1 and Appendix A of ‘The
Elements of Computing Systems: Building a Modern Computer From First Principles’ —
the book which accompanies nand2tetris — when implementing these circuits. You can
find the relevant chapters on their website at: http://nand2tetris.org/course
1. Once you have installed the Software Suite successfully, you will notice within the
“projects/01” folder a number of *.cmp, *.hdl, and *.tst files.
2. Nand is the primitive gate for which all other logic gates are built upon. It is already built-in.
3. More lab reading resources are available at www.nand2tetris.org/01.php. In particular (if
you haven’t already done so, during the first lab session), go to the Resources subsection,
download and go through Part I, II, and III of the Hardware Simulator Tutorial.
4. You should use any standard plain text editor, whichever your favorite editor.
COMP1027 – Computer Fundamentals
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Task A: MyNot, MyAnd, MyOr, MyXor [INDIVIDUAL WORK]
** All implementations, in this task, should use NAND gates ONLY (NAND is Built-in already)
1. Implement the MyNot gate using a single Nand gate. Hint: Both the a and b Nand inputs
can accept a single source input. It would be Nand (a=??, b=??, out=out); Fill in yourself what
?? should be.
2. Implement the MyAnd gate. Hint: Its there inside the lecture notes! But it should be obvious
to you that logically you need a Nand gate connected to a Not gate in sequence.
3. Implement the MyOr gate. Hint: Its there inside the lecture notes! But check the truth table.
4. Implement the MyXor gate.
SUBMISSION: SUBMIT *your* completed MyNot.hdl, MyAnd.hdl, MyOr.hdl, and
MyXor.hdl files. (and all associated testing scripts & compare files). NOTE: we’ll also use our
own test versions during marking.
Task B: MyNot4, MyAnd4, MyOr4 [INDIVIDUAL WORK]
1. Implement the gates; MyNot4, MyAnd4, MyOr4. Hint: you’ll have the same number of inputs,
for each gate, but each input is 4-bits width.
SUBMISSION: SUBMIT *your* completed MyNot4.hdl, MyAnd4.hdl, and MyOr4.hdl file.
(and all associated testing scripts & compare files). NOTE: we’ll also use our own test versions
during marking.
Task C: MyAnd8Way [INDIVIDUAL WORK]
1. Implement the MyAnd8Way. Hint: you have 8 inputs (Ways), each input is a 1-bit width
{later, we’ll also deal with multiple inputs/ways where each input is multi-bits width}. Consider a
binary tree construction of “And” gates (nodes). Drawing the tree would help in visualizing the
implementation. For example, the outputs of two ANDs (each taking in two separate input-pairs)
is fed to the input of another AND higher up in the binary tree. In terms of hdl, this would be
And (a=in[0], b=in[1], out=and01);
And (a=in[2], b=in[3], out=and23);
And (a=and01, b=and23, out=and0123);
COMP1027 – Computer Fundamentals
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You are allowed to use the built-in chips (except the one that you are building off course, or if
you are told otherwise)
SUBMISSION: SUBMIT *your* completed MyAnd8Way.hdl file. (and all associated testing
scripts & compare files). NOTE: we’ll also use our own test versions during marking.
Task D: Plant decision [INDIVIDUAL submission]
1. Implement a chip that produce a decision “Plant or not” based on the various conditions
of the given THREE inputs, as described by the given truth-table below. i.e. F(x,y,z).
SUBMISSION: SUBMIT *your* completed Plant.hdl file. (and all associated testing scripts &
compare files). NOTE: we’ll also use our own test versions during marking.
** You are required to keep your working details (Boolean Function, simplifications,…etc.),
as we can ask you to present it at any time.
Task E: MyHalfadder, MyFulladder [INDIVIDUAL submission]
1. Implement the MyHalfadder. Hint: Check the truth table outputs in your lectures. If you are
still stuck, what about you read Chapter 2?
COMP1027 – Computer Fundamentals
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2. Implement the MyFulladder. Hint: Chapter 2 already mentioned using two HalfAdders.
Obviously, the sum output of the first HalfAdder has to go into one of the inputs of the second
HalfAdder. The sum output of the second HalfAdder is then your FullAdder’s sum output. What
do you do with the carry bits of the two HalfAdders. You need one more logic gate to combine
them. Which one?
SUBMISSION: SUBMIT *your* completed MyHalfadder.hdl and MyFulladder.hdl files.
(No need for testing scripts & compare files for this task. We’ll use ours)
Task F: MyAdd16 and MyInc16 [INDIVIDUAL submission]
1. Implement MyAdd16. Hint: Its mentioned in lectures it is an array of 1-bit FullAdders. How
many of them? The answer is hidden in the name of the adder you are trying to implement!
2. Implement MyInc16. Hint: You just need an adder, specifically Add16. How do you add 1 to
a number given a binary representation?
SUBMISSION: SUBMIT *your* completed MyAdd16.hdl and MyInc16.hdl files. (No need
for testing scripts & compare files for this task. We’ll use ours)
IMPORTANT: See next page for the STRICT submission instructions
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FINAL SUBMISSION INSTRUCTIONS
1. For ALL Tasks, every student should submit his/her own files (listed below).
(remember the “Code of Honor” you signed and submitted)
2. We reserve the right to ask all/some students to explain their submitted work at any time.
Failure to explain it properly could affect your mark.
3. All students must submit on Moodle a ZIP archive containing all their individualworked
files. Name that ZIP file as CSF-Ex1-XXXXXXXX.zip, where XXXXXXXX
is the 8-digits of your student ID.
All the files should be (STRICTLY) in ONE folder and (EXACT) file names, as
below:
{NOTE: marking & checks will be done through scripts, which expects specific file
naming (case sensitive). Any deviation from that will results in errors i.e. losing
marks}
MyNot.hdl MyNot.tst MyNot.cmp
MyAnd.hdl MyAnd.tst MyAnd.cmp
MyOr.hdl MyOr.tst MyOr.cmp
MyXor.hdl MyXor.tst MyXor.cmp
MyNot4.hdl MyNot4.tst MyNot4.cmp
MyAnd4.hdl MyAnd4.tst MyAnd4.cmp
MyOr4.hdl MyOr4.tst MyOr4.cmp
MyAnd8Way.hdl MyAnd8Way.tst MyAnd8Way.cmp
Plant.hdl Plant.tst Plant.cmp
MyHalfadder.hdl
MyFulladder.hdl
MyAdd16.hdl
MyInc16.hdl
In all test & compare files, please present at least 15 different testing cases (if the full truth-table
is longer than that)
Click on the “Ex1” link under “Coursework Submission”. Take note of the
Deadline 16
th
October 2019, 22:00.
Any submission after this, is subject to the usual penalty rule.